STE70NM60
N-CHANNEL 600V - 0.050 - 70A ISOTOP Zener-Protected MDmeshTMPower MOSFET
TYPE STE70NM60 VDSS 600V RDS(on) < 0.055 ID 70 A
YPICAL RDS(on) = 0.050 T H IGH dv/dt AND AVALANCHE CAPABILITIES I MPROVED ESD CAPABILITY L OW INPUT CAPACITANCE AN D GATE C H A R GE L OW GATE INPUT RESISTANCE IGHT PROCESS CONTROL T I NDUSTRY'S LOWEST ON-RESISTANC E DESCRIPTION The MDmeshTM is a new revolutionary MOSFET technology that associates the Multiple Drain process with the C ompany's Pow erMESHTM horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company's proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition's products. APPLICATIONS The MDmeshTM family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies.
I S OT OP
INTERNAL SCHEMATIC DIAGR AM
ORDERING INFORMATION
SALES TYPE STE70NM60 MARKING E70NM60 PACKAGE ISOTOP PACKAGING TUBE
March 2003
1/8
STE70NM60
ABSOLUTE MAXIMUM RA TINGS
Symbol VDS VD G R V GS ID ID ID M ( ) PTOT VESD(G-S) dv/dt (1) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Gate source ESD(HBM-C=100pF, R=15K) Derating Factor Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature Value 600 600 30 70 44 280 600 6 4.5 15 65 to 150 150 Unit V V V A A A W KV W/C V/ns C C
(·)Pulse width limited by safe operating area (1) ISD 70A, di/dt 400 A/s, VDD V(BR)DSS, Tj TJMAX.
THERMAL DATA
Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max Max 0.2 30 300 C/W C/W C
Maximum Lead Temperature For Soldering Purpose
AVA LANCHE CHARACTERISTICS
Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 35 V) Max Value 30 1.4 Unit A J
GATE-SOUR CE ZENER DIODE
Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs= 1mA (Open Drain) Min. 30 Typ. Max. Unit V
PROTECTION FEA TURES OF GATE-TO-SOURCE ZENER DIOD ES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components.
2/8
ST E70N M 60
ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPEC IFIED) ON / OF F
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125C VGS = 20V VDS = VGS, ID = 250 A VGS = 10 V, ID = 30 A 3 4 0.050 Min. 600 10 1 00 10 5 0.055 Typ. Max. Unit V A A A V
DYN AMIC
Symbol gfs (1) Ciss Coss Crss RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Input Resistance Test Conditions VDS = ID(on) x RDS(on)max, ID = 30 A VDS = 25 V, f = 1 MHz, VGS = 0 Min. Typ. 35 7300 2000 40 1.8 Max. Unit S pF pF pF
f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain
SW ITCHIN G ON
Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 300 V, ID = 30 A RG = 4.7 VGS = 10 V (see test circuit, Figure 3) VDD = 470 V, ID = 60 A, VGS = 10 V Min. Typ. 55 95 178 44.5 95 266 Max. Unit ns ns nC nC nC
SW ITCHIN G OFF
Symbol tr(Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 400 V, ID = 60 A, RG = 4.7, VGS = 10 V (see test circuit, Figure 5) Min. Typ. 130 76 105 Max. Unit ns ns ns
SOURCE DR AIN DIODE
Symbol ISD ISDM (2) VSD (1) tr r Q rr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 60 A, VGS = 0 ISD = 60 A, di/dt = 100 A/s, VDD = 30 V, Tj = 150C (see test circuit, Figure 5) 600 14 48 Test Conditions Min. Typ. Max. 60 240 1.5 Unit A A V ns C A
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area.
3/8
STE70NM60
Safe Operating A rea Thermal Impedance
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
4/8
ST E70N M 60
Gate Charge vs Gate-source Voltage Capacitance Variations
Normalized Gate Threshold Voltage vs Temp.
Normalized On Resistance vs Temperature
Source-drain Diode Forward C haracteristics
Normalized BVDSS vs Temperature
5/8
STE70NM60
Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive W aveform
Fig. 3: Switching Times Test Circuit For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test C ircuit For Inductive Load Switching And Diode Recovery Times
6/8
ST E70N M 60
ISOTOP MECHANICAL DATA
DIM. MIN. A B C D E F G H J K L M N O 11.8 8.9 1.95 0.75 12.6 25.15 31.5 4 4.1 14.9 30.1 37.8 4 7.8 8.2 4.3 15.1 30.3 38.2 mm TYP. MAX. 12.2 9.1 2.05 0.85 12.8 25.5 31.7 MIN. 0.466 0.350 0.076 0.029 0.496 0.990 1.240 0.157 0.161 0.586 1.185 1.488 0.157 0.307 0.322 0.169 0.594 1.193 1.503 inch TYP. MAX. 0.480 0.358 0.080 0.033 0.503 1.003 1.248
G O B
A
N
D
E
J K L M
H
C
F
7/8
STE70NM60
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
8/8
|
